View AX88141_8003773.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

asix electronics corporation 2f, no.13, industry east rd. ii, science-based industrial park, hsin-chu city, taiwan, r.o.c. tel: 886-3-579-9500 fax: 886-3-579-9558 http:/www.asix.com.tw AX88141 fast ethernet mac controller asix asix AX88141 100base-tx/fx pci bus fast ethernet mac controller with power management data sheet (4/11/ ? 98) document no. : ax141-01.doc this data sheets contain new products information. asix electronics reserves the rights to modify the products specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. always contact asix for possible updates before starting a design.
AX88141 preliminary asix electronics corporation 2 confidential contents 1.0 introduction ................................ ................................ ................................ ................................ .......... 6 1.1 g eneral d escription : ................................ ................................ ................................ ................................ 6 1.2 f eatures ................................ ................................ ................................ ................................ ..................... 7 1.3 b lock d iagram : ................................ ................................ ................................ ................................ .......... 8 1.4 AX88141 p in c onnection d iagram ................................ ................................ ................................ ........... 9 2.0 signal description ................................ ................................ ................................ ............................. 10 2.1 s ignal d escriptions ................................ ................................ ................................ ................................ . 10 2.2 pci interface group ................................ ................................ ................................ ................................ . 10 2.3 b oot rom , s erial rom , g eneral - purpose signals group ................................ ................................ .. 11 2.4 mii interface signals group ................................ ................................ ................................ ................... 12 2.5 p ower pins group ................................ ................................ ................................ ................................ ...... 13 3.0 configuration operation ................................ ................................ ................................ ............. 14 3.1 c onfiguration s pace m apping ................................ ................................ ................................ ................ 14 3.2 c onfiguration s pace ................................ ................................ ................................ ............................... 15 3.2.1 configuration id register (csid) ................................ ................................ ................................ ....... 15 3.2.2 command and status configuration register (cscs) ................................ ................................ ........... 15 3.2.3 configuration revision register (csrv) ................................ ................................ ............................. 15 3.2.4 configuration latency timer register (cslt) ................................ ................................ .................... 15 3.2.5 configuration base i/o address register (cbio) ................................ ................................ ............... 16 3.2.6 configuration base memory address register (cbma) ................................ ................................ ...... 16 3.2.7 expansion rom base address register (cber) ................................ ................................ ................. 16 3.2.8 configuration interrupt register (csit) ................................ ................................ .............................. 16 3.2.9 special use register (sud) ................................ ................................ ................................ ................ 16 3.2.10 subsystem id and subsystem vendor register (ssid) ................................ ................................ ....... 16 3.2.11 new capabilities pointer (cncp) ................................ ................................ ................................ ..... 17 3.2.12 power management register block (offset 44h to 49h) ................................ ................................ ...... 17 4.0 registers operation ................................ ................................ ................................ ......................... 18 4.1 r egisters m apping ................................ ................................ ................................ ................................ ... 18 4.2 h ost reg s ................................ ................................ ................................ ................................ ................ 19 4.2.1 bus mode register (reg0) ................................ ................................ ................................ .................. 19 4.2.2 magic packet password low (reg0b) ................................ ................................ ................................ 19 4.2.3 transmit poll demand (reg1) ................................ ................................ ................................ ........... 19 4.2.4 magic packet password high (reg1b) ................................ ................................ .............................. 19 4.2.5 receive poll demand (reg2) ................................ ................................ ................................ ............. 20 4.2.6 receive list base address (reg3) ................................ ................................ ................................ ...... 20 4.2.7 transmit list base address (reg4) ................................ ................................ ................................ .... 20 4.2.8 status register (reg5) ................................ ................................ ................................ ....................... 21 4.2.9 operation mode register (reg6) ................................ ................................ ................................ ....... 22 4.2.10 interrupt enable register (reg7) ................................ ................................ ................................ ..... 24 4.2.11 missed frame and overflow counter (reg8) ................................ ................................ .................. 24 4.2.12 serial rom and mii management register (reg9) ................................ ................................ .......... 25 4.2.13 general -purpose timer (reg11) ................................ ................................ ................................ ..... 25 4.2.14 general -purpose port register (reg12) ................................ ................................ .......................... 26 4.2.15 filtering index (reg13) ................................ ................................ ................................ ................... 26 4.2.16 filtering data (reg14) ................................ ................................ ................................ ..................... 26 5.0 host communication ................................ ................................ ................................ ........................ 28 5.1 d escriptor l ists and d ata b uffers ................................ ................................ ................................ ........ 28 5.2 r eceive d escriptors ................................ ................................ ................................ ................................ 29 5.2.1 receive descriptor 0 (rdes0) ................................ ................................ ................................ ............. 29
AX88141 preliminary asix electronics corporation 3 confidential 5.2.2 receive descriptor 1 (rdes1) ................................ ................................ ................................ ............. 30 5.2.3 receive descriptor 2 (rdes2) ................................ ................................ ................................ ............. 30 5.2.4 receive descriptor 3 (rdes3) ................................ ................................ ................................ ............. 30 5.3 t ransmit d escriptors ................................ ................................ ................................ .............................. 31 5.3.1 transmit descriptor 0 (tdes0) ................................ ................................ ................................ ............ 31 5.3.2 transmit descriptor 1 (tdes1) ................................ ................................ ................................ ............ 32 5.3.3 transmit descriptor 2 (tdes2) ................................ ................................ ................................ ............ 32 5.3.4 transmit descriptor 3 (tdes3) ................................ ................................ ................................ ............ 32 6.0 electrical specification and timings ................................ ................................ .................. 33 6.1 a bsolute m aximum r atings ................................ ................................ ................................ .................... 33 6.2 g eneral o peration c onditions ................................ ................................ ................................ .............. 33 6.3 dc c haracteristics ................................ ................................ ................................ ................................ . 33 6.4 a.c. t iming c haracteristics ................................ ................................ ................................ ................... 34 6.4.1 pci clock ................................ ................................ ................................ ................................ ......... 34 6.4.2 pci timings ................................ ................................ ................................ ................................ ......... 34 6.4.3 reset timing ................................ ................................ ................................ ................................ ........ 34 6.4.4 mii timing ................................ ................................ ................................ ................................ ........... 35 6.4.5 boot rom read cycles ................................ ................................ ................................ ....................... 36 7.0 package information ................................ ................................ ................................ ...................... 37 appendix a h/w note ................................ ................................ ................................ ....................... 38 a.1 b oot rom read cycle ................................ ................................ ................................ ............................ 38 a.2 p ower s upply ................................ ................................ ................................ ................................ ........... 39 a.3 b oundary s can t est p ins ................................ ................................ ................................ ....................... 39 appendix b function application ................................ ................................ ........................... 40 b.1 a pplication for pci i nterface ................................ ................................ ................................ ............... 40 b.2 a pplication for b oot rom i nterface ................................ ................................ ................................ ... 41 b.3 a pplication for s erial rom i nterface ................................ ................................ ................................ . 41 b.4 a pplications ................................ ................................ ................................ ................................ ............ 42 b.4.1 application for ns dp83843 ................................ ................................ ................................ ............... 42 b.4.2 application for lucent m-lu6612/m-3x51 ................................ ................................ ..................... 42 b.4.3 application for ti xtnete2101 ................................ ................................ ................................ ......... 43
AX88141 preliminary asix electronics corporation 4 confidential figures f ig - 1 AX88141 b lock d iagram ................................ ................................ ................................ ..... 8 f ig - 2 AX88141 p in connection diagram ................................ ................................ ...................... 9 f ig - 3 d escriptor s tructure e xample ................................ ................................ ........................... 28 f ig - 4 r eceive d escriptor f ormat ................................ ................................ ................................ . 29 f ig - 5 t ransmit d escriptor f ormat ................................ ................................ ............................... 31 f ig - 6 a pplication for lxt970 ................................ ................................ ................................ ..... 42 f ig - 7 a pplication for mtd972 +mtd971 ................................ ................................ ............... 43 f ig - 8 a pplication for dm9101 ................................ ................................ ................................ ..... 43
AX88141 preliminary asix electronics corporation 5 confidential tables t ab - 1 pci interface group ................................ ................................ ................................ .............................. 11 t ab - 2 b oot rom , s erial rom , g eneral - purpose signals group ................................ ............................... 12 t ab - 3 mii interface signals group ................................ ................................ ................................ ................. 12 t ab - 4 p ower pins group ................................ ................................ ................................ ................................ ... 13 t ab - 5 c onfiguration s pace m apping ................................ ................................ ................................ .............. 14 t ab - 6 csid c onfiguration id r egister d escription ................................ ................................ .................... 15 t ab - 7 cscs c ommand and s tatus c onfiguration r egister ................................ ................................ ........ 15 t ab - 8 csrv c onfiguration r evision r egister d escription ................................ ................................ ......... 15 t ab - 9 cslt c onfiguration id r egister d escription ................................ ................................ ................... 15 t ab - 10 cbio c onfiguration b ase i/o a ddress r egister d escription ................................ ......................... 16 t ab - 11 cbma c onfiguration b ase m emory a ddress r egister d escription ................................ .............. 16 t ab - 12 cber e xpansion rom b ase a ddress r egister d escription ................................ ............................ 16 t ab - 13 csit c onfiguration i nterrupt r egister d escription ................................ ................................ ...... 16 t ab - 14 csit c onfiguration i nterrupt r egister d escription ................................ ................................ ...... 16 t ab - 15 ssid c onfiguration id r egister d escription ................................ ................................ .................. 17 t ab - 16 cncp c onfiguration id r egister d escription ................................ ................................ ................. 17 t ab - 17 csid c onfiguration id r egister d escription ................................ ................................ .................. 17 t ab - 18 c ommand and s tatus r egister m apping ................................ ................................ ............................ 18 t ab - 19 reg0 b us m ode r egister d escription ................................ ................................ ............................... 19 t ab - 20 reg1 t ransmit p oll d emand r egister d escription ................................ ................................ ........ 19 t ab - 21 reg1 t ransmit p oll d emand r egister d escription ................................ ................................ ........ 19 t ab - 22 reg1 t ransmit p oll d emand r egister d escription ................................ ................................ ........ 19 t ab - 23 reg2 r eceive p oll d emand r egister d escription ................................ ................................ ........... 19 t ab - 24 reg3 r eceive l ist b ase a ddress r egister d escription ................................ ................................ ... 20 t ab - 25 reg4 t ransmit l ist b ase a ddress r egister d escription ................................ ................................ 20 t ab - 26 reg5 s tatus r egister d escription ................................ ................................ ................................ .... 22 t ab - 27 reg6 o peration m ode r egister d escription ................................ ................................ ................... 23 t ab - 28 p ort and d ata r ate s election ................................ ................................ ................................ ........... 23 t ab - 29 reg7 i nterrupt e nable r egister d escription ................................ ................................ ................. 24 t ab - 30 reg8 m issed f rame and o verflow c ounter d escription ................................ ............................... 24 t ab - 31 reg9 s erial rom, and mii m anagement r egister d escription ................................ .................... 25 t ab - 32 reg11 g eneral -p urpose t imer r egister d escription ................................ ................................ ..... 26 t ab - 33 reg12 g eneral -p urpose p ort r egister d escription ................................ ................................ ....... 26 t ab - 34 reg13 f iltering i ndex r egister d escription ................................ ................................ ................... 26 t ab - 35 reg14 f iltering d ata r egister d escription ................................ ................................ .................... 26 t ab - 36 d escription of f iltering b uffer ................................ ................................ ................................ ........ 26 t ab - 37 l ayout of f iltering b uffer ................................ ................................ ................................ ................ 27 t ab - 38 r eceive d escriptor 0 ................................ ................................ ................................ ........................... 30 t ab - 39 r eceive d escriptor 1 ................................ ................................ ................................ ........................... 30 t ab - 40 r eceive d escriptor 2 ................................ ................................ ................................ ........................... 30 t ab - 41 r eceive d escriptor 3 ................................ ................................ ................................ ........................... 30 t ab - 42 t ransmit d escriptor 0 ................................ ................................ ................................ ........................ 32 t ab - 43 t ransmit d escriptor 1 ................................ ................................ ................................ ........................ 32 t ab - 44 t ransmit d escriptor 2 ................................ ................................ ................................ ........................ 32 t ab - 45 t ransmit d escriptor 3 ................................ ................................ ................................ ........................ 32
AX88141 preliminary asix electronics corporation 6 confidential 1.0 introduction 1.1 general description: l the AX88141 fast ethernet controller is a high performance and highly integrated pci bus ethernet controller chip. l the AX88141 is cost effective, high performance solution for pci add-in adapters, pc motherboards, or bridge/hub applications. l it implements both 10mbps and 100mbps ethernet function based on ieee802.3 u lan standard. l the AX88141 contains a high speed 32 bit pci bus master interface to host cpu. two large independent transmit and receive fifo allow the AX88141 to buffer the ethernet packet efficiently. l the AX88141 support 10mbps / 100mbps media-independent interface (mii) to simplify the design. l the AX88141 is compliant with the network device class power management and the communication device class power management requirements under the onnow architecture for pc 97 and pc 98. l the AX88141 is compliant with the advanced configuration and power interface (acpi) specification and the pci bus power management interface specification. l the AX88141 provide both phy level or mac level power management function. l the AX88141 provide magic packet algorithm with password to support acpi function.
AX88141 preliminary asix electronics corporation 7 confidential 1.2 features l single chip pci bus fast ethernet controller. l direct interface to pci bus. l support both 10mbps and 100mbps data rate. l full or half duplex operation supported for both10mbps and 100mbps operation. l provides a mii port for both 10/100mbps operation. l support 20mhz to 33mhz no wait state pci bus interface. l two large independent fifo for transmit and receive. no additional on board buffer memory required. l interface to serial rom for ethernet id address and jumper-less board design. l 6 4 kb boot rom support. l support automatic loading of subvendor id. l on chip general purpose, programmable register and i/o pins. l unlimited pci burst. l external and internal loop-back capability. l support early interrupts on transmit. l powerful on chip buffer management dma. and pci bus master operation reduce cpu utilization. l support network device onnow requirements for pc 97 and pc 98. l compliant with the acpi specification and the pci bus power management interface specification. l support magic packet technology. l big and little endian byte ordering supported. l ieee 802.3u 100base-t, tx, and t4 compatible. l 128 pin pqfp package. l 5v cmos process.
AX88141 preliminary asix electronics corporation 8 confidential 1.3 block diagram: serial boot rom rom interface pci mii bus general purpose i/o pins fig - 1 AX88141 block diagram boot rom i/f serial rom i/f receive fifo transmit fifo buffer management dma engine mac controller 10/100 mii interface general purpose reg pci bus interface
AX88141 preliminary asix electronics corporation 9 confidential 1.4 AX88141 pin connection diagram the AX88141 is housed in the 1 28 -pin plastic quad flat pack. fig - 2 shows the AX88141 pin connection diagram. fig - 2 AX88141 pin connection diagram ad_1 br_d6 ad_13 devsel# ad_20 c_be#3 ad_26 txd_0 int# br_d3 123 118 122 78 70 64 54 41 32 24 12 8 vdd br_d7 vss ad_19 ad_25 vdd mdio ad_2 br_a15 117 75 57 42 26 31 21 vss br_d5 vdd vss pme# txd_1 col vss rxd_2 107 105 66 65 63 60 25 16 13 3 7 sr_ck ad_15 vss txd_2 rxclk vdd ad_5 128 115 112 61 33 br_ce# c_be#1 ad_29 111 43 19 15 4 br_a0 ad_7 par trdy# req# ad_21 vdd 109 106 77 62 11 6 vss vdd frame# ad_16 gnt# br_d2 serr# 71 49 17 ad_9 vss idsel ad_23 vdd br_a14 68 58 56 55 45 23 ad_0 c_be#0 stop# irdy# vss pci_clk rxer 53 116 113 59 36 34 1 ad_12 ad_28 vss crs gep_0 br_d1 vss 124 108 vss vdd perr# ad_17 vdd ad_27 ad_30 vdd mdc txclk rxd_3 rxd_1 28 22 9 sr_do/br_d0 vdd ad_18 rst# vss sr_di rxd_0 126 119 110 121 79 74 ad_4 ad_10 ad_22 80 72 46 29 52 10 sr_cs txen rxdv gep_1 ad_6 67 44 39 27 51 5 ad_8 ad_11 br_d4 127 125 120 114 73 69 38 48 vdd vss ad_14 ad_24 ad_31 76 47 35 30 20 2 ad_3 vss c_be#2 vss ptest vss txd_3 vss 40 37 50 18 14 AX88141 103 104 82 91 81 86 93 94 84 87 95 96 90 88 92 85 89 83 98 97 99 100 102 101 br_a13 br_a12 br_a11 br_a10 br_a9 br_a8 br_a7 br_a6 br_a5 br_a4 br_a3 br_a2 br_a1
AX88141 preliminary asix electronics corporation 10 confidential 2.0 signal description 2.1 signal descriptions the following terms describe the a x88141 pin-out: l address phase address and appropriate bus commands are driven during this cycle. l data phase data and the appropriate byte enable codes are driven during this cycle. l # all pin names with the # suffix are asserted low. the following abbreviations are used in tab - 1 pci interface group tab - 2 boot rom , serial rom , general- purpose signals group , tab - 3 mii interface signals group , tab - 4 power pins group .. i input o output i/o input /output o/d open drain 2.2 pci interface group signal type pin number description cbe#<3> cbe#<2> cbe#<1> cbe#< 0> i/o 21, 38, 48, 61 bus command and byte enable a re multiplexed on the same pci pins . d uring the address phase of the transaction , cbe#<3:0> p rovide the bus command. d uring the data phase , cbe#<3:0> p rovide the byte enable. t he byte enable determines which byte lines carry valid data ., cbe#<0> a pplies to byte 0, and cbe#<3> a pplies to byte 3. devsel# i/o 42 d evice select i s asserted by the target of the current bus access . w hen the AX88141 is the master of the current bus access, the target assert devsel# confirming the access . i t is driven by AX88141 w hen AX88141 is selected as a slave. frame# i/o 39 t he frame# s ignal is driven by the AX88141 t o indicate the beginning and duration of an access. frame# a sserts to indicate the beginning of a bus transaction . w hile frame# is asserted, data transfers continue. w hen frame# deasserts the next data phase is the final data phase transaction. gnt# i 7 bus grant i ndicates to the AX88141 t hat access to the bus is granted. idsel i 22 i nitialization devise select asserts t o indicate that the host is issuing a configuration cycle to the AX88141. int# o/d 1 i nterrupt request asserts w hen one of the appropriate bits of reg5 sets and causes an interrupt, provided that the corresponding mask bit in reg7 is not asserted. interrupt request deasserts by writing a 1 into the appropriate reg5 bit. t his pin must be pulled up by an external resistor. irdy# i/o 40 i nitiator ready i ndicates the bus master ability to complete the current data phase of the transaction. a data phase is completed on any rising edge of the clock w hen both irdy# and target ready trdy# are asserted . w ait cycles are inserted until both irdy# and trdy# are asserted together. w hen the AX88141 is the bus master, irdy# is asserted during write operations to indicate that valid data is present on the ad<31:0>. d uring read operations, the AX88141 asserts irdy# to indicate that it is ready to accept data. par i/o 47 p arity is an even parity bit for the ad<31:0> ad and cbe#<3:0>. d uring address and data phases, parity is calculated on all the ad<31:0> and cbe#<3:0> lines whether or not any of these lines carry meaningful information.
AX88141 preliminary asix electronics corporation 11 confidential ad<31> ad<30> ad<29> ad<28> ad<27> ad<26> ad<25> ad<24> ad<23> ad<22> ad<21> ad<20> ad<19> ad<18> ad<17> ad<16> ad<15> ad<14> ad<13> ad<12> ad<11> ad<10> ad<9> ad<8> ad<7> ad<6> ad<5> ad<4> ad<3> ad<2> ad<1> ad<0> i/o 10, 11, 13, 14, 16, 17, 19, 20, 24, 25, 26, 27, 29, 30, 33, 34, 50, 51, 52, 54, 55, 57, 58, 59, 62, 63, 64, 66, 67, 69, 70, 72 address and data bits are multiplexed on the same pins. during the address phase, the ad<31:0> contain a physical address (32 bits). during, data phases, ad<31:0> contain 32 bits of data. the AX88141 supports both read and write bursts (in master operation only). little and big endian byte ordering can be used. pci_clk i 5 t he clock provides the timing for the AX88141 related pci bus transactions . a ll the bus signals are sampled on the rising edge of pci_clk. t he clock frequency range is between 20mhz and 33mhz. perr# i/o 45 p arity error asserts when a data parity error is detected . w hen the AX88141 is the bus master it monitor perr# to see if the target report a data parity error., when the AX88141 is the bus target and a parity error is detected, the AX88141 asserts perr#. t his pin must be pulled up by an external resistor. req# o 8 b us request is asserted by the AX88141 to indicate to the bus arbiter that it wants to use the bus . rst# i 2 r esets the AX88141 to its initial state . t his signal must be asserted for at least 10 active pci clock cycles . w hen is the reset state, all pci output pins are put into tri-state and all pci o/d signals are floated. serr# i/o 46 system error is used by AX88141 to report address parity error. this pin must be pulled up by an external resistor. stop# i/o 43 stop indicator indicates that the current target is requesting the bus master to stop the current transaction. the AX88141 responds to the assertion of stop# when it is the bus master, and stop the current transaction. trdy# i/o 41 target ready indicates the target ability to complete the current data phase of the transaction. a data phase is completed on any clock when both trdy# and irdy# are asserted. wait cycles are inserted until both irdy# and trdy# are asserted together. when the AX88141 is the bus master, target ready is asserted by the bus slave on the read operation, indicating that valid data is present on the ad lines. during a write cycle, it indicates that the target is prepared to accept data. pme# o 9 tab - 1 pci interface group 2.3 boot rom , serial rom , general-purpose signals group signal type pin number description
AX88141 preliminary asix electronics corporation 12 confidential br_a<15> br_a<14> br_a<13> br_a<12> br_a<11> br_a<10> br_a<9> br_a<8> br_a<7> br_a<6> br_a<5> br_a<4> br_a<3> br_a<2> br_a<1> br_a<0> o 104, 103, 102, 101, 100, 99, 98, 97, 96, 95, 94, 93, 92, 91, 90, 89 boot rom address lines bit 15 to bit 0. br_d<7> br_d<6> br_d<5> br_d<4> br_d<3> br_d<2> br_d<1> br_d<0>/ sr_do i 88, 86, 85, 84, 83, 82, 81, 73 boot rom data lines bit 7 to bit 0. serial rom data-out signal. br_ce# o 78 boot rom chip enable. sr_ck o 76 serial rom clock signal. sr_cs o 77 serial rom chip-select signal. sr_di o 79 serial rom data-in signal. genp<1> genp<0> i/o 106, 105 general-purpose pins can be used by software as either status pins or control pins. these pins can be configured by software to perform either input or output functions. tab - 2 boot rom , serial rom , general-purpose signals group 2.4 mii interface signals group signal type pin number for 160 pin description col i 113 c ollision detected is asserted when detected by an external physical layer protocol (phy) device . crs i 114 c arrier sense is asserted by the phy when the media is active. rxdv i 111 d ata valid is asserted by an external phy when receive data is present on the rxd lines and is deasserted at the end of the packet . t his signal should be synchronized with the rxclk signal . rxer i 109 r eceive error asserts when a data decoding error is detected by an external phy device . t his signal is synchronized to rxclk and can be asserted for a minimum of one receive clock . w hen asserted during a packet reception, it sets the cyclic redundancy check (crc) error bit in the receive descriptor ( rdeso). mdc o 108 mii management data clock is sourced by the AX88141 to the phy devices as a timing reference for the transfer of information on the mii_mdio signal . mdio i/o 107 mii management data input/output transfers control information and status between the phy and the AX88141. rxclk i 115 s upports either the 25-mhz or 2.5-mhz receive clock . t his clock is recovered by the phy. rxd<3> rxd<2> rxd<1> rxd<0> i 119, 118, 117, 116 f our parallel receive data lines w hen mii mode is selected . t his data is driven by an external phy that attached the media and should be synchronized with the rxclk signal . txclk i 121 s upports the 25-mhz or 2.5-mhz transmit clock supplied by the external physical layer medium dependent (pmd) device . t his clock should always be active. txd<3> txd<2> txd<1> txd<0> o 128, 127, 125, 124 f our parallel transmit data lines . t his data is synchronized to the assertion of the txclk signal and is latched by the external phy on the rising edge of the txclk signal . txen o 123 t ransmit enable signals that the transmit is active to an external phy device. tab - 3 mii interface signals group
AX88141 preliminary asix electronics corporation 13 confidential 2.5 power pins group signal type pin number description vdd p 3,18,28,31,44,56, 68,75,80,110,120, 126 5-v supply input voltage . vss p 4,6,12,15,23,32, 35,37,49,53,60, 65,71,74,87,112, 122 ground pins. tab - 4 power pins group
AX88141 preliminary asix electronics corporation 14 confidential 3.0 configuration operation 1. software reset (reg0<0>) has no effect on the configuration registers. 2. hardware reset puts the configuration registers in default values. 3. the configuration registers could be accessed in byte, word , and long-word. 3.1 configuration space mapping configuration register identifier i/o address offset device/vendor id csid 00h command and status cscs 04h revision csrv 08h latency timer cslt 0ch base i/o address cbio 10h base memory address cbma 14h reserved - 18h-28h subsystem/subvendor id ssid 2ch expansion rom base address cber 30h new capabilities pointer cncp 34h reserved - 38h interrupt csit 3ch special use sud 40h power management cpmr 44h - 49h tab - 5 configuration space mapping
AX88141 preliminary asix electronics corporation 15 confidential 3.2 configuration space 3.2.1 configuration id register (csid) field r/w description 31:16 r device id : provides the unique AX88141 id number (1400h) 15:0 r vender id : provides the manufacturer of the AX88141 (125bh) tab - 6 csid configuration id register description 3.2.2 command and status configuration register (cscs) field r/w type description 31 r status detected parity error : active high 30 r status signal system error : active high 29 r status received master abort : active high 28 r status received target abort : active high 26:25 r status device select timing : fixed at 01 which indicates a medium assertion of devsel# 24 r status data parity report : active high 23 r status fast back-to-back : always set 22:21 - reserved 20 r status cpapbility of power management : always set. 19-9 - reserved 8 r/w command system error enable : active high 6 r/w command parity error response : active high 2 r/w command master operation : active high 1 r/w command memory space access : active high 0 r/w command i/o space access : active high tab - 7 cscs command and status configuration register 3.2.3 configuration revision register (csrv) field r/w description 31:24 r base class : always equal to 2h that indicates the network controller 23:16 r subclass : always equal to 0h that indicates the fast ethernet controller 7:4 r revision number : indicates the AX88141 revision number and is equal to 1h 3:0 r step number : indicates the AX88141 step number and is referred to current silicon step. tab - 8 csrv configuration revision register description 3.2.4 configuration latency timer register (cslt) field r/w description 31:16 r/w reserved 15:8 r/w configuration latency timer. the value after hardware reset equal to 0h. 7:0 r/w reserved tab - 9 cslt configuration id register description
AX88141 preliminary asix electronics corporation 16 confidential 3.2.5 configuration base i/o address register (cbio) field r/w description 31:7 r/w configuration base i/o address : defines the address assignment mapping of AX88141 ? s regs. 6:1 r this field value is 0 when read 0 r i/o space indicator : determines that the register maps into the i/o space. the value in this field is 1. tab - 10 cbio configuration base i/o address register description 3.2.6 configuration base memory address register (cbma) field r/w description 31:7 r/w configuration base memory address : defines the address assignment mapping of AX88141 ? s regs. 6:1 r this field value is 0 when read 0 r memory space indicator : determines that the register maps into the memory space. the value in this field is 0. tab - 11 cbma configuration base memory address register description 3.2.7 expansion rom base address register (cber) field r/w description 31:10 r/w expansion rom base address 9:1 r this field value is 0 when read 0 r/w expansion rom enable bit : active high tab - 12 cber expansion rom base address register description 3.2.8 configuration interrupt register (csit) field r/w description 31:24 r max_lat : time unit is equal to 0.25 microsecond. (28h) 23:16 r min_gnt : t ime unit is equal to 0.25 microsecond. (14h) 15:8 r interrupt pin : the AX88141 uses inta# and the read value is (01h). 7:0 r/w interrupt line : the bios writes the routing information into this field. tab - 13 csit configuration interrupt register description 3.2.9 special use register (sud) field r/w description 31:30 r reserved 29 r/w enable bit, when set to ? 1 ? , if gep link pin has transition, pme# will active. 28 r/w this bit will be ? 1 ? if gep link pin has transitions. 27 r/w this bit will be ? 1 ? if magic packet was detected. 26-25 r reserved 24 r/w password enable bit, when this bit is set to ? 1 ? , ax881401 will check the password from magic packet with the stored password in reg 0b and reg 1b before asserting the magic packet detected bit (<3> of reg 43) 23-16 r reserved 15:8 r/w driver special use 7-0 r reserved tab - 14 csit configuration interrupt register description 3.2.10 subsystem id and subsystem vendor register (ssid) field r/w description 31:16 r subdsystem id : provides the subsystem id which is loaded from eeprom at hardware reset 15:0 r subsystem vender id : provides the subsystem vendor id which is loaded from eeprom at hardware reset.
AX88141 preliminary asix electronics corporation 17 confidential tab - 15 ssid configuration id register description 3.2.11 new capabilities pointer (cncp) field r/w description 7:0 r new capabilities pointer : point to power management registers starting address, value is 44h tab - 16 cncp configuration id register description 3.2.12 power management register block (offset 44h to 49h) offset r/w description 44h r capability id : the value is 01h to indicate power management block. 45h r next item pointer : the value is 00h to indicate this is the last block 46h r power management capabilities, : the value is 21h to indicate version 1.0 of pci power management specification and need a device specific initialization sequence following transition to the do uninitialized state 47h r power management capabilities : the value is 48h to indicate pme# support from do and d3 hot state. 48-49h r/w power management status : <15> : pme# status -- set when the function would normally assert the pme# signal independent of the state of the pme# pin enable bit. write a ? 1 ? to this bit will clear it and cause the function to stop asserting a pme# (if enabled). write a ? 0 ? no effect. when reset default is ? 0 ? . <8> : pme# pin enable control bit -- a ? 1 ? enable the function to assert pme#. writing a ? 0 ? pme# assertion is disabled. when reset default is ? 0 ? <1:0> : power state -- only 00 (d0) and 11 (d3) supported tab - 17 csid configuration id register description
AX88141 preliminary asix electronics corporation 18 confidential 4.0 registers operation 1. the regs are quad-word aligned, 32-bits long, and must be accessed using long-word instruction with quad-word aligned addresses only. 2. reserved bits should be written with 0.; reserved bits are unpredictable on read access. 3. retries on second data transactions occur in response to burst accesses. 4.1 registers mapping register meaning offset from reg base address (cbio,cbma) reg0 bus mode 00h reg0b magic packet password low <31:0> 04h reg1 transmit poll demand 08h reg1b magic packet password high <47:32> 0ch reg2 receive poll demand 10h reg3 receive list base address 18h reg4 transmit list base address 20h reg5 status 28h reg6 operation mode 30h reg7 interrupt enable 38h reg8 missed frame and overflow counter 40h reg9 serial rom, and mii management 48h reg10 - 50h reg11 general-purpose timer 58h reg12 general-purpose port 60h reg13 filtering buffer index 68h reg14 filtering buffer data 70h reg14b reserved 74h reg15 reserved 78h reg15b reserved 7ch tab - 18 command and status register mapping
AX88141 preliminary asix electronics corporation 19 confidential 4.2 host regs 4.2.1 bus mode register (reg0) field r/w/c description 31:22 - reserved 21 r/w rml - read multiple when set, the AX88141 supports the memory-read-multiple command on the pci bus. this bus command is used in memory read bursts with more than one longword. when reset, the AX88141 uses memory-read command in all its memory read accesses on the pci bus. 20 r/w dbo - descriptor byte ordering mode when set, the AX88141 operates in big edian ordering mode for descriptors only . when reset, the AX88141 operates in little endian mode. 19:14 - reserved.--written as ? 0 ? for future compatibility concern. 13:8 r/w pbl - programmable burst length indicates the maximum number of longwords to be transfered in one dma transaction. if reset, the AX88141 burst is limited only by the amount of data stored in the receive fifo (at least 16 longword), or by the amount of free space in the transmit fifo (at least 16 longword) before issuing a bus request. the pbl can be programmed with permissible values 0,1,2,4,8,16, or 32. after reset, the pbl default value is 0. 7 r/w ble - big/little endian when set, the AX88141 operates in big endian byte ordering mode. when reset, the AX88141 operates in little endian byte ordering mode. big endian is applicable only for data buffer 6:2 - reserved 1 r/w bar - bus arbitration selects the internal bus arbitration between the receive and transmit processes. when set, a round robin arbitration scheme is applied resulting in equal sharing between processes. when reset, the receive process has priority over the transmit process, unless the AX88141 is currently transmitting. 0 r/w swr - software reset when set, the AX88141 resets all internal hardware with the exception of the configuration area and also, it does not change the port select setting (reg6<18>). software reset does not affect the configuration area. tab - 19 reg0 bus mode register description 4.2.2 magic packet password low (reg0b) field r/w description 31:0 r/w mppl - magic packet password low this register contains the magic packet password bits 31 to 0. tab - 20 reg1 transmit poll demand register description 4.2.3 transmit poll demand (reg1) field r/w description 31:0 w tpd - transmit poll demand when written with any value, the AX88141 checks for frames to be transmitted. if no descriptor is available, the transmit process returns to the suspended states and reg5<2> is asserted. if the descriptor is available the transmit process resumes. tab - 21 reg1 transmit poll demand register description 4.2.4 magic packet password high (reg1b) field r/w description 31:16 r reserved 15:0 r/w mpph - magic packet password high this register contains the magic packet password bits 47 to 32. tab - 22 reg1 transmit poll demand register description
AX88141 preliminary asix electronics corporation 20 confidential 4.2.5 receive poll demand (reg2) field r/w/c description 31:0 w rpd - receive poll demand when written with any value, the AX88141 checks for receive descriptors to be required. if no descriptor is available, the receive process returns to the suspended states and reg5<7> is not asserted. if the descriptor is available the receive process resumes. tab - 23 reg2 receive poll demand register description 4.2.6 receive list base address (reg3) 1. the register is used to point the AX88141 to the start of receive descriptors list. 2. the descriptor list resides in physical memory space and must be longword aligned. the AX88141 behaves unpredictably when the list are not longword aligned. 3. writing to reg3 is permitted only when receive process is in the stopped state. that is, the reg3 must be written before the receive start command is given . reg3 receive list base address register description field r/w/c description 31:2 r/w start of receive list 1:0 r/w must be 00 for longword alignment tab - 24 reg3 receive list base address register description 4.2.7 transmit list base address (reg4) 1. the register is used to point the AX88141 to the start of transmit descriptors list. 2. the descriptor list resides in physical memory space and must be long-word aligned. the AX88141 behaves unpredictably when the list are not long-word aligned. 3. writing to reg4 is permitted only when transmit process is in the stopped state. that is, the reg4 must be written before the transmit start command is given . field r/w/c description 31:2 r/w s tart of transmit list 1:0 r/w must be 00 for long-word alignment tab - 25 reg4 transmit list base address register description
AX88141 preliminary asix electronics corporation 21 confidential 4.2.8 status register (reg5) 1. the status register contains all the status bits that the AX88141 reports to the host. 2. most of the fields in this register cause the host to be interrupted. 3. reg5 bits are not cleared when read. 4. writing 1 to these bits clears them; writing 0 has no effect. each field can be masked. field r/w/c description 31:26 - reserved 25 24 23 description 0 0 0 parity error 0 0 1 master abort 0 1 0 target abort 0 1 1 reserved 25:23 r eb - error bits (not generate interrupt) indicates the type of error that caused system error. valid only when fatal bus error reg5<13> is set. 1 x x reserved 22:20 - reserved.--written as ? 0 ? for future compatibility concern. 19:17 - reserved.--written as ? 0 ? for future compatibility concern. nis - normal interrupt summary only the unmasked bits affect normal interrupt summary reg5<16> bit normal interrupt summary bit. its value is the logical or of : csr5<0> transmit interrupt csr5<2> transmit buffer unavailable csr5<6> receive interrupt csr5<10> early transmit interrupt 16 r csr5<11> general-purpose timer expired ais - abnormal interrupt summary only unmasked bits affect only the abnormal interrupt summary reg5<15> bit. abnormal interrupt summary bits. its value is the logical or of : csr5<1> transmit process stopped csr5<3> transmit jabber time out csr5<5> transmit under-flow csr5<7> receive buffer unavailable csr5<8> receive process stopped csr5<9> receive watchdog time out 15 r csr5<13> fatal bus error 13 r fbe - fatal bus error indicates that a system error occurred. if a system error occurs, all bus accesses are disabled 11 r/w/c gte - general purpose timer expired indicates that the general-purpose timer (reg11) counter has expired. this timer is mainly used by the software driver. 10 r/w/c eti - early transmit interrupt indicates that the packet to be transmitted was fully transferred into the chip ? s internal transmit fifos. transmit interrupt (reg5<0>) automatically clears this bit. 9 r/w/c rwt - receive watchdog time out indicates that the receive watchdog timer expired and another node is still active on the network. in case of overflow, the long packets may not be received. 8 r/w/c rps - receive process stopped asserts when the receive process enters stopped state. 7 r/w/c ru - receive buffer unavailable indicates the next descriptor in the receive list is owned by the host and cannot be acquired by the AX88141.the reception process is suspended. 6 r/w/c ri - receive interrupt indicates the completion of a frame reception. specific frame status information has been posted in the descriptor. the reception process remains in the running state. 5 r/w/c unf - transmit under-flow indicates that the transmit fifo had an under-flow condition during the packet transmission. the transmit process is placed in the suspended state and under-flow error tdes0<1> is set. 4 - reserved.--written as ? 0 ? for future compatibility concern.
AX88141 preliminary asix electronics corporation 22 confidential 3 r/w/c tjt - transmit jabber time-out indicates that the transmit jabber timer expired, meaning that the AX88141 transmitter had been excessively active. the transmission process is aborted and placed in the stopped state. this event causes the transmit jabber time-out tdes0<14> is set. 2 r/w/c tu - transmit buffer unavailable indicates that the next descriptor on the transmit list is owned by the host and cannot be acquired by the AX88141.the transmission process is suspended. to resume processing transmit descriptors, the host should change the ownership bit of the descriptor and then issue a transmit poll demand command. 1 r/w/c tps - transmit process stopped asserts when the transmit process enters the stopped state. 0 r/w/c ti - transmit interrupt indicates that a frame transmission was completed, while tdes1<31> is asserted in the first descriptor of the frame. tab - 26 reg5 status register description 4.2.9 operation mode register (reg6) 1. reg6 establishes the receive and transmit operating modes and commands. 2. reg6 should be the last reg to be written as part of initialization. field r/w/c description 31 - reserved 1 all incoming packets will be received 30 r/w ra - receive all 0 filtering mode 29:23 - reserved.--written as ? 0 ? for future compatibility concern. 1 threshold is 10mb/s 22 r/w ttm - transmit threshold mode 0 threshold is 100mb/s 1 enable store and forward 21 r/w sf - store and forward 0 disable store and forward 20 - reserved.--written as ? 0 ? for future compatibility concern. 1 heartbeat disable 19 r/w hbd - heartbeat disable 0 heartbeat enable 1 mii port is selected. 18 r/w ps - port select 0 n/a 17:16 - reserved.--written as ? 0 ? for future compatibility concern. tr - threshold control bits the threshold value has a direct impact on the AX88141 bus arbitration scheme . transmission starts when the frame size within the transmit fifo is larger than the threshold. in addition, full frames with a length less than the threshold are also transmitted. the transmit process must be in the stopped state to change these bits. controls the selected threshold level for the AX88141 transmit fifo. four threshold levels are allowed. reg6<18>=0 reg6<18>=1 reg6<18>=1 reg6<21> reg6<15:14> reg6<22>=x reg6<22>=1 reg6<22>=0 15:14 r/w 0 00 72 72 128 0 01 96 96 256 0 10 128 128 512 0 11 160 160 1024 1 xx store & forward store & forward store & forward 1 start transmission 13 r/w st - start/stop transmission 0 stop transmission 1 enable force collision 12 r/w fc - force collision mode 0 disable force collision 00 normal 01 internal loop-back 11:10 r/w om - operating mode 10 external loop-back 1 full-duplex 9 r/w fd - full-duplex mode 0 half-duplex 1 accept broadcast packet 8 r/w rb - receive broadcast packet 0 reject broadcast packet 1 enable pass all multicast 7 r/w pm - pass all multicast 0 disable pass all multicast 6 r/w pr - promiscuous mode 1 indicates that any incoming valid frame is received, regardless of its destination address.
AX88141 preliminary asix electronics corporation 23 confidential 0 disable promiscuous mode. 5:4 - reserved.--written as ? 0 ? for future compatibility concern. 1 all incoming frames that passed the address filtering are received, including runt frames, collided fragments, or truncated frames caused by fifo over-flow. if any received bad frames are required, promiscuous mode (reg6<6>) should be set to 1. 3 r/w pb - pass bad frames 0 disable pass bad frame. 2 - reserved.--written as ? 0 ? for future compatibility concern. 1 start receive 1 r/w sr - start/stop receive 0 stop receive 1 AX88141 mode. 0 r/w fifo mode 0 ax88140 mode. tab - 27 reg6 operation mode register description port and data rate selection reg6 <18> reg6 <22> active port data rate function 1 1 mii 10mb/s mii with transmit fifo thresholds appropriate for 10mb/s 1 0 mii 100mb/s mii with transmit fifo thresholds appropriate for 100mb/s tab - 28 port and data rate selection
AX88141 preliminary asix electronics corporation 24 confidential 4.2.10 interrupt enable register (reg7) 1. the interrupt enable register (reg7) enables the interrupts reported by reg5. 2. setting bit to 1 enables a corresponding interrupt. after a hardware or software reset, all interrupts are disabled. field r/w/c description 31:17 - reserved ni - normal interrupt summary enable when set, normal interrupt is enabled. when reset, no normal interrupt is enabled. this bit (reg7<16>) enables the following bits : csr5<0> transmit interrupt csr5<2> transmit buffer unavailable csr5<6> receive interrupt csr5<10> early transmit interrupt 16 r/w csr5<11> general-purpose timer expired ai - abnormal interrupt summary enable when set, abnormal interrupt is enabled. when reset, no abnormal interrupt is enabled. this bit (reg7<15>) enables the following bits : csr5<1> transmit process stopped csr5<3> transmit jabber time-out csr5<5> transmit under-flow csr5<7> receive buffer unavailable csr5<8> receive process stopped csr5<9> receive watchdog time-out 15 r/w csr5<11> fatal bus error 13 r/w fbe - fatal bus error interrupt enable. active high. 11 r/w gpt - general purpose timer interrupt enable. active high. 10 r/w ete - early transmit interrupt enable. active high. 9 r/w rw - receive watchdog time out interrupt enable. active high 8 r/w rs - receive stopped interrupt enable. active high. 7 r/w ru - receive buffer unavailable interrupt enable. active high. 6 r/w ri - receive interrupt enable. active high. 5 r/w un - under-flow interrupt enable. active high. 4 - reserved.--written as ? 0 ? for future compatibility concern. 3 r/w tj - transmit jabber time out interrupt enable. active high. 2 r/w tu - transmit buffer unavailable interrupt enable. active high. 1 r/w ts - transmission stopped interrupt enable. active high. 0 r/w ti - transmit interrupt enable. active high. tab - 29 reg7 interrupt enable register description 4.2.11 missed frame and overflow flag (reg8) field r/w description 31: 18 - r eserved 17 r/c o verflow flag i ndicates the frames discarded because of overflow . t he flag clears when read. 16 : 1 - r eserved 0 r/c missed frame flag indicates the frames discarded because no host receive descriptors were available. the flag clears when read. tab - 30 reg8 missed frame and overflow counter description
AX88141 preliminary asix electronics corporation 25 confidential 4.2.12 serial rom and mii management register (reg9) 1. the register provides an interface to the microwire serial rom and to the physical layer protocol (phy). it selects the device and contains both the commands and data to be read from and stored in the serial rom. 2. the mii management selects and operation mode for reading and writing the mii. field r/w/c description 31:20 - reserved.--written as ? 0 ? for future compatibility concern. 19 r mdi - mii management data_in u sed by the AX88141 to read data from the phy 18 r/w mii - mii management operation mode d efines the operation mode (read or write) of the phy. 17 r/w mdo - mii m anagement write data s pecifies the value of the data that AX88141 writes to the phy 16 r/w mdc - mii m anagement clock mii management data clock (mii_mdc) is an output signal to the phy. it is used as a timing reference. 14 r/w rd - r ead operation r ead control bit. w hen set together with reg9<12>, t he AX88141 performs read cycles from the boot rom, and the serial rom. 13:12 - reserved.--written as ? 0 ? for future compatibility concern. 11 r/w sr - s erial rom select w hen set together with either serial rom read operation (reg9<14>) or serial rom w rite operation (reg9<13>), t he AX88141 selects the serial rom. 10:4 - reserved.--written as ? 0 ? for future compatibility concern. 3 r/w sdo - serial rom data_out serial rom data output (sr_do) f rom the serial rom device to the AX88141. 2 r sdi - serial rom data_in serial rom d ata input (sr_di) t o the serial rom device from the AX88141. 1 r/w sclk - serial rom serial clock s erial clock (sr_ck) o utput to the serial rom. 0 r/w scs - serial rom chip select chip select (sr_cs) output to the serial rom. tab - 31 reg9 serial rom, and mii management register description 4.2.13 general -purpose timer (reg11) 1. this register contains a 16 bit general-purpose timer. it is used mainly by the software driver for timing functions not supplied by the operating system. after the timer is loaded, it starts counting down . the expiration of the timer causes an interrupt in reg5<11>. 2. if the timer expires with the con bit on, the counter will load itself automatically with the last value. the timer is not active in snooze mode. field r/w/c description 31:17 - reserved.--written as ? 0 ? for future compatibility concern. 1 continuous operating mode. 16 r/w con - continuous mode 0 one-shot operating mode. 15:0 r/w timer value contains the general-purpose timer value within a n microsecond cycle. srl_10m : 204.8us mii_10m : 819.2us mii_100m : 81.92us
AX88141 preliminary asix electronics corporation 26 confidential tab - 32 reg11 general -purpose timer register description 4.2.14 general -purpose port register (reg12) field r/w/c description 31:9 - reserved.--written as ? 0 ? for future compatibility concern. 1 indicate next write reg12<7:0> is use for define general purpose port in/out direction. 8 r/w gpc - general purpose control . when a hardware reset is initiated, all gep pins become input pins. 0 indicate next write reg12<7:0> is use for read/write general purpose port data. 7:0 r/w md - general purpose mode and data tab - 33 reg12 general -purpose port register description 4.2.15 filtering index (reg13) field r/w/c description 31:6 - reserved.--written as ? 0 ? for future compatibility concern. 5:0 r/w fi - filtering index when writing data to filtering buffer, uses filtering index register reg13 to point the position (buffer number) in filtering buffer. the valid value is between 0 and 3. tab - 34 reg13 filtering index register description 4.2.16 filtering data (reg14) field r/w/c description 31:0 r/w fd - filtering data by indexed by filtering index register reg13, write the filtering data register reg14 to put filtering address/hash table into filtering buffer.. tab - 35 reg14 filtering data register description filtering buffer the AX88141 stores one ethernet address for local physical address and filters the packets with multicast addresses by 64 bits array. for any incoming frame with a multicast destination address, the AX88141 applies the standard ethernet cyclic redundancy check function to the destination address, then uses the most significant 6 bits of the result as a bit index into the table. if the indexed bit is set, the frame is accepted. if the bit is reset, the frame is rejected. description of filtering buffer buffer number description 0 byte 0 - 3 of local physical address 1 byte 4 - 5 of local physical address in the least significant word 2 bit 0 - 31 of multicast address filtering table 3 bit 32 - 63 of multicast address filtering table tab - 36 description of filtering buffer layout of filtering buffer buffer number byte 3 byte 2 byte 1 byte 0 0 physical address byte 3 physical address byte 2 physical address byte 1 physical address byte 0
AX88141 preliminary asix electronics corporation 27 confidential 1 reserved reserved physical address byte 5 physical address byte 4 2 multicast address filtering table bit 24 - 31 multicast address filtering table bit 16 - 23 multicast address filtering table bit 8 - 15 multicast address filtering table bit 0 - 7 3 multicast address filtering table bit 56 - 63 multicast address filtering table bit 48 - 55 multicast address filtering table bit 40 - 47 multicast address filtering table bit 32 - 39 tab - 37 layout of filtering buffer
AX88141 preliminary asix electronics corporation 28 confidential 5.0 host communication descriptor lists and data buffers, collectively called the host communication, reside in the host memory and manage the actions and status related to buffer management. 5.1 descriptor lists and data buffers the AX88141 transfers data frames to the receive buffers and from the transmit buffers in host memory. descriptors that reside in the host memory act as pointers to these buffers. there are two descriptor lists, one for receive and one for transmit. the base address of each list is written into reg3 and reg4, respectively. a descriptor list is forward-linked (explicitly). the last descriptor may point back to the first entry to create a ring structure. explicit chaining of descriptors is accomplished by setting the address pointer chained in both the receive and transmit descriptors (rdes3 and tdes3). the descriptor lists reside in the host physical memory address space. a data buffer consists of either an entire frame or part of a frame, but it cannot exceed a single frame. buffers contain only data; buffer status is maintained in the descriptor. data chaining refers to frames that span multiple data buffers. descriptor structure example next descriptor fig - 3 descriptor structure example buffer 1 descriptor 0 buffer 2 descriptor 1
AX88141 preliminary asix electronics corporation 29 confidential 5.2 receive descriptors the receive descriptor provides one buffer, one byte-count buffer, and one address pointer in each descriptor. descriptors and receive buffers addresses must be long-word aligned. receive descriptor format 31 0 rdes0 o w n status rdes1 control bits byte count buffer 2 byte count buffer 1 rdes2 buffer address 1 rdes3 buffer address 2 fig - 4 receive descriptor format 5.2.1 receive descriptor 0 (rdes0) rdes0 contains the received frame status, the frame length, and the descriptor ownership information. field description 1 indicates that the descriptor is owned by the AX88141 31 own - own bit the AX88141 clears this bit either when it completes the frame reception or when the buffers that are associated with this descriptor are full. 0 indicates that the descriptor is owned by the host 1 indicates that the frame failed the address recognition filtering 30 ff - filtering fail this bit can be set only when receive all (reg6<30>) is set. 0 indicates that the frame passed the address recognition filtering 29:16 fl - frame length indicates the length in bytes of the received frame including the cyclic redundancy check (crc). this field is valid only when last descriptor (rdes0<8>) is set and descriptor error ( rdes0<14>) is reset. es - error summary indicates the logical or of the following rdes0 bits : this field is valid only when last descriptor (rdes0<8>) is set. rdes0<1> crc error rdes0<6> collision seen rdes0<7> frame too long rdes0<11> runt frame 15 rdes0<14> descriptor error 14 de - descriptor error. the frame is truncated. active high. this field is valid only when last descriptor (rdes0<8>) is set. 13:12 reserved.--written as ? 0 ? for future compatibility concern. 11 rf - runt frame. indicates that this frame is a runt frame. active high. this field is valid only when last descriptor (rdes0<8>) is set .
AX88141 preliminary asix electronics corporation 30 confidential 10 mf - multicast frame indicates that this frame is a multicast address. this field is valid only when last descriptor (rdes0<8>) is set. 1 indicates that this descriptor contains the first buffer of a frame. 9 fs - first descriptor 0 indicates that this descriptor is the middle or last buffer of a frame. 1 indicates that the buffers pointed to by this descriptor, are the last buffers 8 ls - last descriptor 0 indicates that this descriptor is the middle or first buffer of a frame. 7 tl - frame too long. frame length grater then 1518 bytes. active high. this field is valid only when last descriptor (rdes0<8>) is set. 6 cs - collision seen. this is a late collision. this field is valid only when last descriptor (rdes0<8>) is set. 5 reserved.--written as ? 0 ? for future compatibility concern. 4 rw ? received first packet flag after receiver buffer unavailable state is cleared. 3 re - report on mii error. active high. 2 db - dribbling bit active high. if set, and crc error (rdes0<1>) is reset, then the packet is valid. 1 ce - crc error. active high. this field is valid only when last descriptor (rdes0<8>) is set. 0 fifo overrun. active high. tab - 38 receive descriptor 0 5.2.2 receive descriptor 1 (rdes1) field description 31:11 reserved.--written as ? 0 ? for future compatibility concern. 10:0 rbs - receive data buffer size indicates the size in bytes of the data buffer. if this field is 0, the AX88141 ignores this buffer. the buffer size must be a multiple of 4. tab - 39 receive descriptor 1 5.2.3 receive descriptor 2 (rdes2) field description 31:0 data buffer pointer indicates the physical address of data buffer. the buffer must be long-word-aligned (rdes2<1:0>=00). tab - 40 receive descriptor 2 5.2.4 receive descriptor 3 (rdes3) field description 31:0 address pointer indicates the physical address of next descriptor. the address must be long-word aligned (rdes3<1:0>=00). tab - 41 receive descriptor 3
AX88141 preliminary asix electronics corporation 31 confidential 5.3 transmit descriptors providing one buffer, one byte-count buffer, and two address pointers in each descriptor . transmit descriptor format 31 0 tdes0 o w n status tdes1 control bits byte count buffer 2 byte count buffer 1 tdes2 buffer address 1 tdes3 buffer address 2 fig - 5 transmit descriptor format 5.3.1 transmit descriptor 0 (tdes0) tdes0 contains transmitted frame status and descriptor ownership information. field description 1 indicates that the descriptor is owned by the AX88141. 31 own - own bit 0 indicates that the descriptor is owned by the host. 30:16 reserved.--written as ? 0 ? for future compatibility concern. es - error summary indicates the logical or of the following bits : tdes0<1> under-flow error tdes0<8> successive collisions tdes0<9> late collision tdes0<10> no carrier tdes0<11> loss of carrier 15 tdes0<14> transmit jabber time-out 14 to - transmit jabber time-out : active high. the transmission process is aborted and placed in the stopped state. when tdes0<14> is set any heartbeat fail indication (tdes0<7>) is not valid. 13:12 reserved.--written as ? 0 ? for future compatibility concern. 11 lo - loss of carrier during transmission. active high. (the status is no meaning except 10base srl mode) not valid in internal loop-back mode (reg6<11:10>=01). 10 nc - no carrier. indicates that the carrier signal from the transceiver was not present during transmission. active high. not valid in internal loop-back mode (reg6<11:10>=01). 9 lc - late collision. when set, indicates that the frame transmission was aborted due to collision occurring after the collision window of 64 bytes. not valid if under-flow error (tdes0<1>) is set. 8 ec - excessive collision when set, indicates that the transmission was aborted after 16 successive collisions while attempting to transmit the current frame. 7 hf - heartbeat fail this bit is effective only in 10mb/s operation mode. when set, indicates a heartbeat collision check failure this bit is not valid if under-flow error (tdes0<1>) is set. on the second transmission attempt, after the first transmission was aborted due to collision, the AX88141 does not check heartbeat fail and (tdes0<7>) is reset. 6:3 cc - collision count this 4-bit counter indicates the number of collisions that occurred before the frame was transmitted. not valid when the excessive collisions bit (tdes0<8>) is also set. 2 reserved.--written as ? 0 ? for future compatibility concern.
AX88141 preliminary asix electronics corporation 32 confidential 1 uf - under-flow error when set, indicates that the transmitter aborted the message because data arrived late from memory. under-flow error indicates that the AX88141 encountered an empty transmit fifo while transmitting a frame. the transmission process enters the suspended state and sets both transmit under-flow (reg5<0>) and transmit interrupt (reg5<0>). 0 de - deferred when set, indicates that the AX88141 had to defer while ready to transmit a frame because the carrier was asserted. tab - 42 transmit descriptor 0 5.3.2 transmit descriptor 1 (tdes1) field description 31 ic - interrupt on completion when set, the AX88141 sets transmit interrupt (reg5<0>) after the present frames has been transmitted. it is valid only when first segment (tdes1<30>) is set. 1 indicates that the buffer contains the last segment of a frame. 30 ls - last segment 0 indicates that the buffer contains the first or middle segment of a frame. 1 indicates that the buffer contains the first segment of a frame. 29 fs - first segment 0 indicates that the buffer contains the middle or last segment of a frame. 28:27 reserved.--written as ? 0 ? for future compatibility concern. 26 ac - add crc disable when set, the AX88141 does not append the crc to the end of the transmitted frame. this field is valid only when first segment (tdes1<29>) is set. 25:24 reserved.--written as ? 0 ? for future compatibility concern. 1 the AX88141 does not automatically add a padding field, so a packet shorter than 64 bytes. 23 dpd - disabled padding the crc field is added despite the state of the add crc disable (tdes1<26>) flag. 0 the AX88141 automatically adds a padding field and also a crc field to a packet shorter than 64 bytes. 22:11 reserved.--written as ? 0 ? for future compatibility concern. 10:0 data buffer size indicates the size, in bytes, of the data buffer. if this field is 0, the AX88141 ignores this buffer. tab - 43 transmit descriptor 1 5.3.3 transmit descriptor 2 (tdes2) field description 31:0 data buffer pointer physical address of data buffer. there are no limitations on the buffer address alignment. tab - 44 transmit descriptor 2 5.3.4 transmit descriptor 3 (tdes3) field description 31:0 address pointer physical address of next descriptor address. there are no limitation on the buffer address alignment. tab - 45 transmit descriptor 3
AX88141 preliminary asix electronics corporation 33 confidential 6.0 electrical specification and timings 6.1 absolute maximum ratings description sym min max units operating temperature ta 0 +70 c storage temperature ts -55 +150 c supply voltage vcc -0.5 +7 v input voltage vin vss-0.5 vdd+0.5 v output voltage vout vss-0.5 vdd+0.5 v lead temperature (soldering 10 seconds maximum) tl -55 +250 c note : stress above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended period, adversely affect device life and reliability 6.2 general operation conditions description sym min max units operating temperature ta 0 +70 c supply voltage vdd +4.75 +5.25 v 6.3 dc characteristics (vdd=4.75v to 5.25v, vss=0v, ta=0 c to 70 c) description sym min tpy max units low input voltage vil vss-0.5 0.8 v high input voltage vih 2 vdd+0.5 v low output voltage vol - 0.4 v high output voltage voh 2.4 - v input leakage current 1 (note 1) iil1 - 10 ua input leakage current 2 (note 2) iil1 - 500 ua output leakage current iol - 10 ua power consumption ( sleep ,note 3 ) ps 18 ma power consumption ( idle , driver loaded ) pi 72 ma power consumption ( heavy traffic ) pt 110 ma note : 1. all the input pins without pull low or pull high. 2. those pins had been pull low or pull high. 3. when sleep mode, pci clock stop / link on ; if link off, typical is 2.5ma .
AX88141 preliminary asix electronics corporation 34 confidential 6.4 a.c. timing characteristics 6.4.1 pci clock symbol description min typ. max units t cyc cycle time 30 - 45 ns t high pci_clk high time 11 - - ns t low pci_clk low time 11 - - ns t r/ t f pci_clk slew rate 1 - 4 ns 6.4.2 pci timings pci_clk tval tval (max) (min) output ton toff input tsu th symbol description min typ. max units t val clk to signal valid delay 2 - 11 ns t on float to active delay 2 - - ns t off active to float delay - - 28 ns t su input setup time to clk 7 - - ns t h input hold time from clk 0 - - ns 6.4.3 reset timing pci_clk rst# symbol description min typ. max units trst reset pulse width 10 - - pci clk
AX88141 preliminary asix electronics corporation 35 confidential 6.4.4 mii timing ttclk ttch ttcl txclk ttv tth txd<3:0> txen trclk trch trcl rxclk trs trh rxd<3:0> rxdv trs1 rxer symbol description min typ. max units ttclk cycle time(100mbps) - 40 - ns ttclk cycle time(10mbps) - 400 - ns ttch high time(100mbps) 14 - 26 ns ttch high time(10mbps) 140 - 260 ns trch low time(100mbps) 14 - 26 ns trch low time(10mbps) 140 - 260 ns ttv clock to data valid - - 20 ns tth data output hold time 5 - - ns trclk cycle time(100mbps) - 40 - ns trclk cycle time(10mbps) - 400 - ns trch high time(100mbps) 14 - 26 ns trch high time(10mbps) 140 - 260 ns trcl low time(100mbps) 14 - 26 ns trcl low time(10mbps) 140 - 260 ns trs data setup time 6 - - ns trh data hold time 10 - - ns trs1 rxer data setup time 10 - - ns
AX88141 preliminary asix electronics corporation 36 confidential 6.4.5 boot rom read cycles boot rom byte read cycle br_d<7:0> data br_a<15:0> address br_ce# boot rom dword read cycle br_d<7:0> data3 data2 data1 data0 br_a<15:0> addr3 addr2 addr1 addr0 br_ce#
AX88141 preliminary asix electronics corporation 37 confidential 7.0 package information b e d hd e he pin 1 a2 a1 l l1 q milimeter symbol min. nom max a1 0. 21 0. 31 0. 41 a2 2. 8 0 2. 85 2. 9 0 b 0.15 0.20 0.30 d 13.80 14.00 14.20 e 19.80 20.00 20.20 e 0.5 0 hd 1 7 . 1 0 1 7 . 2 0 1 7 .30 he 2 3 . 1 0 2 3 . 2 0 2 3 .30 l 0. 7 0 0. 8 0 0. 9 0 l1 1. 6 0 q 0 8
AX88141 preliminary asix electronics corporation 38 confidential appendix a h/w note a.1 boot rom read cycle asix 88141 boot rom byte read cycle br_d<7:0> data br_a<15:0> address br_ce# a0 q0 a1 q1 a2 q2 a3 q3 a4 q4 a5 q5 a6 q6 a7 q7 a8 a9 a10 a11 a12 a13 a14 a15 /ce /oe 27512 br_a0 br_a1 br_a2 br_a3 br_a4 br_a5 br_a6 br_a7 br_a8 br_a9 br_a10 br_a11 br_a12 br_a13 br_a14 br_a15 br_d0 br_d1 br_d2 br_d3 br_d4 br_d5 br_d6 br_d7 br_ce# gnd dec 21140 boot rom byte read cycle: br_ad<7:0> address 7-2 address 15-8 data br_a1 address 1 br_a0 address 17 address16 address 0 brce# d0 q0 d1 q1 d2 q2 d3 q3 d4 q4 d5 q5 d6 q6 d7 q7 oc clk 74ls374 d0 q0 d1 q1 d2 q2 d3 q3 d4 q4 d5 q5 d6 q6 d7 q7 oc clk 74ls374 a8 a9 a10 a11 a12 a13 a14 a15 gnd bra1 gnd brad0 brad1 brad2 brad3 brad4 brad5 brad6 brad7 a0 q0 a1 q1 a2 q2 a3 q3 a4 q4 a5 q5 a6 q6 a7 q7 a8 a9 a10 a11 a12 a13 a14 a15 /ce /oe 27512 bra0 bra1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 brad0 brad1 brad2 brad3 brad4 brad5 brad6 brad7 br_ce /oe /we /oe a2 a3 a4 a5 a6 a7
AX88141 preliminary asix electronics corporation 39 confidential a.2 power supply AX88141 power supply is +5v dc dec 21140 power supply is +3.3v dc a.3 boundary scan test pins AX88141 do not support boundary scan test pins dec 21140 supports boundary scan test pins
AX88141 preliminary asix electronics corporation 40 confidential appendix b function application b.1 application for pci interface features : l direct interface to pci bus. l support 33 mhz no wait state pci bus interface. l powerful on chip buffer management dma. and pci bus master operation reduce cpu utilization. l 5 volt cmos process. pci interface schematic: pci bus connector AX88141 pci i/o pins ad[31:0] c/be[3:0] par pci slot mac frame# trdy# irdy# stop# devsel# idsel perr# serr# req# gnt# clk rst# pme# the pull high resisters are required for pin req#, gnt#, perr#, and serr# on mac for more detail please to check the schematic.
AX88141 preliminary asix electronics corporation 41 confidential b.2 application for boot rom interface AX88141 boot rom byte read cycle br_d<7:0> data br_a<15:0> address br_ce# a0 q0 a1 q1 a2 q2 a3 q3 a4 q4 a5 q5 a6 q6 a7 q7 a8 a9 a10 a11 a12 a13 a14 a15 /ce /oe 27512 br_a0 br_a1 br_a2 br_a3 br_a4 br_a5 br_a6 br_a7 br_a8 br_a9 br_a10 br_a11 br_a12 br_a13 br_a14 br_a15 br_d0 br_d1 br_d2 br_d3 br_d4 br_d5 br_d6 br_d7 br_ce# gnd b.3 application for serial rom interface AX88141 serial rom chip select serial rom serial rom clock serial rom interface serial rom data in 93c46 serial rom data out
AX88141 preliminary asix electronics corporation 42 confidential b.4 applications b.4.1 application for ns dp83843 fig - 6 application for ns dp83843 b.4.2 application for lucent m-lu6612/m-3x51 fig - 7 application for lucent m-lu6612 mii sta AX88141 mac controller mii 10base-t transceiver lucent m-lu6612 /m-3x51 a.n. 4b/5b scrambler / descrambler st 6166 x ? former rj-45 mii sta AX88141 mac controller mii 10base-t transceiver ns dp83843 phy a.n. 4b/5b scrambler / descrambler st 6114 x ? former rj-45
AX88141 preliminary asix electronics corporation 43 confidential b.4.3 application for ti xtnete2101 fig - 8 application for ti xtnete2101 mii sta AX88141 mac controller mii 10base-t transceiver ti xtnete2101 a.n. 4b/5b scrambler / descrambler ycl 20pmt04 x ? former rj-45

▲Up To Search▲

Price & Availability of AX88141

	To Download AX88141 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .